1. Field of the Invention
The present invention relates to a failure detection improvement apparatus, a medium being readable by a computer and having a failure detection improvement program allowing a computer to execute a failure detection improvement method that modifies a net list recorded thereon, and a failure detection improvement method that improve failure detection rate in circuit verification.
2. Description of the Related Art
In LSI (Large Scale Integrated Circuit) manufacturing process, an ATPG (Automatic Test Pattern Generator) tool is used to automatically generate a test pattern, and the circuit is tested using the test pattern and a verification tool, thereby checking whether there is any failure in a product, and if there is no failure, the product is shipped to market.
As a conventional art related to the present invention, a test facilitation design rule examination apparatus disclosed in Jpn. Pat. Appln. Laid-Open Publication No. 2000-148813 is known, for example. The test facilitation design rule examination apparatus computes the rate of failure detection performed using the ATPG tool in a test facilitation design rule examination to thereby increase design efficiency.
However, the circuit includes a part where the test pattern cannot be generated by the ATPG tool. In the following two types of circuits, the ATPG tool cannot generate the test pattern.
The first circuit is a circuit fixed by a test mode signal. In generating the test pattern using the ATPG tool, some parts in the circuit need to be fixed. A signal value is fixed in the circuit that follows the first circuit, so that it is not possible to detect a failure. For example, in an enable clock buffer called GCKB (Gated Clock Buffer) used for achieving low power consumption in LSI, an enable signal is fixed in a test mode, and the output clock of GCKB is not allowed to be stopped. When a test mode signal flows in, a generation circuit of the enable signal is masked by a mask-cell. Therefore, the ATPG tool cannot generate the test pattern for detecting a failure in the generation circuit. Further, in the case where the test mode signal is used as a select signal and an input terminal having a fixed value in a test mode is selected in a selector, it is impossible to generate a test pattern for detecting a failure in a circuit connected to another input terminal.
The second circuit is a circuit with deep logic, where the number of logic stages provided between FFs (flip-flop) has exceeds the number of logic stages that the ATPG tool can analyze. The ATPG tool sets a value for the front stage FF and observes the value of the rear stage FF, thereby generating a test pattern for verifying logic of the circuit between FFs. However, deep logic makes it difficult to control the value of FF, with the result that the ATPG tool cannot generate a test pattern.
In the case where the ATPG tool cannot generate a test pattern as described above, a user checks a part where the ATPG tool cannot detect a failure with reference to a failure list, which is the execution result of the ATPG tool, and creates a test pattern for that part. However, an increase in the circuit scale of LSI and complexity in the function thereof makes it difficult for the ATPG tool to generate a test pattern, as well as for the user to create a test pattern for the part where a failure cannot be automatically detected. Accordingly, failure detection rate has been decreased.